<--- Back to Details
First PageDocument Content
Cache / Computer performance / Software optimization / Cell / CPU cache / Lookup table / Loop fusion / Reuse / Program optimization / Computing / Compiler optimizations / Computer architecture
Date: 2008-09-16 13:24:23
Cache
Computer performance
Software optimization
Cell
CPU cache
Lookup table
Loop fusion
Reuse
Program optimization
Computing
Compiler optimizations
Computer architecture

A Tuning Framework for Software-Managed Memory Hierarchies Manman Ren Stanford University

Add to Reading List

Source URL: theory.stanford.edu

Download Document from Source Website

File Size: 1,04 MB

Share Document on Facebook

Similar Documents

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE/ACM TRANSACTIONS ON NETWORKING 1  Milking the Cache Cow With Fairness

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE/ACM TRANSACTIONS ON NETWORKING 1 Milking the Cache Cow With Fairness

DocID: 1xVD7 - View Document

CacheQuote: Efficiently Recovering Long-term Secrets of SGX EPID via Cache Attacks

CacheQuote: Efficiently Recovering Long-term Secrets of SGX EPID via Cache Attacks

DocID: 1xVnr - View Document

RobinHood: Tail Latency-Aware Caching Dynamically Reallocating from Cache-Rich to Cache-Poor Daniel S. Berger (CMU) Joint work with: Benjamin Berg (CMU), Timothy Zhu (PennState), Siddhartha Sen (Microsoft Research), Mor

RobinHood: Tail Latency-Aware Caching Dynamically Reallocating from Cache-Rich to Cache-Poor Daniel S. Berger (CMU) Joint work with: Benjamin Berg (CMU), Timothy Zhu (PennState), Siddhartha Sen (Microsoft Research), Mor

DocID: 1xV9M - View Document

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

Learning gem5 – Part III Modeling Cache Coherence with Ruby and SLICC Jason Lowe-Power http://learning.gem5.org/ https://faculty.engineering.ucdavis.edu/lowepower/

DocID: 1xUst - View Document

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

DocID: 1xUq9 - View Document