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Tagged memory and minion cores in the lowRISC SoC December 2014 lowRISC project team Computer Laboratory
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Document Date: 2015-05-13 16:22:20

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Computer Laboratory University of Cambridge lowRISC-MEMO / /

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capability systems / security applications / minimal software / low-speed protocols / legacy software / software analyses / complicated software-supported tagging / deterministic real-time processing / tagged memory solution / wireless network processor / implemented using fixed-function hardware / software techniques / software hooks / energy usage / energy consumption / reconfigurable hardware / software-defined peripherals / test chips / software transactional memory implementation / test chip / higher speed protocols / cross site / /

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Time Processor Unit / Programmable Unit for Metadata Processing / USENIX Association / Programmable Real-Time Unit / Computer Laboratory University of Cambridge lowRISC-MEMO / IEEE Computer Society / /

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Programmable Memory Controller for the DDRx Interfacing Standards” / O Tag Cache Memory Controller / Programmable Memory Controller / memory controller / /

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