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Memory Access Optimized Routing Scheme for Deep Networks on a Mobile Coprocessor
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Document Date: 2015-03-07 08:16:31


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Bath / New York / /

Company

Neural Information Processing Systems / Neural Networks / Deep Convolutional Neural Networks / GPU / A. Computational Resources / AAAI Press / Artificial Neural Networks / NVIDIA / Xilinx / Intel / /

Country

United States / /

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pence / USD / /

Facility

Purdue University / /

IndustryTerm

non-linear operator / layer network / memory router / energy-based learning / host processor / parallel digital learning processor / the resources in the hardware / synthetic vision systems / real-time applications / real time / wearable support systems / large networks / document processing / security systems / stream processors / real-time implementation / convolutional networks / layer networks / cots hpc systems / real-world applications / vision applications / optimized software libraries / similar algorithms / vision systems / purpose processors / runtime reconfigurable dataflow processor / image processing / real-time processing / baseline application processor / recent algorithms / /

Organization

office of Naval Research / Rectified Linear Unit / Purdue University / Analysis and Machine Intelligence / US Federal Reserve / Weldon School of Biomedical Engineering / /

Person

I. Durdanovic / V / L. Van Gool / M. Sankaradas / V / J. Jin / V / Eugenio Culurciello / /

Product

CPU / a NVIDIA GeForce GTX 690 GPU / Torch7 software / CPU / Torch7 / /

PublishedMedium

Machine Learning / /

Technology

fpga-based processor / FPGA / ARM processor / memory router / cache memory / ARM Cortex A9 processor / mobile phones / machine learning / html / shared memory / image processing / massively parallel digital learning processor / runtime reconfigurable dataflow processor / host processor / artificial intelligence / Programmable stream processors / purpose processors / baseline application processor / parallel processing / /

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