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Electronic design automation / Logic design / Model checking / Temporal logic / VHDL / Logic simulation / Hardware verification languages / Formal methods / Property Specification Language / Electronic engineering / Digital electronics / Hardware description languages
Date: 2013-10-21 02:25:05
Electronic design automation
Logic design
Model checking
Temporal logic
VHDL
Logic simulation
Hardware verification languages
Formal methods
Property Specification Language
Electronic engineering
Digital electronics
Hardware description languages

ON THE EFFECTIVENESS OF ASSERTION-BASED VERIFICATION IN AN INDUSTRIAL CONTEXT L.Pierre, F.Pancher, R.Suescun, J.Quévremont TIMA Laboratory, Grenoble, France

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