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Central processing unit / Microprocessors / CPU cache / Cache / Computer memory / Scheduling / Microarchitecture / Thread / Parallel computing / Computing / Computer architecture / Computer hardware


Spatially Aware Decentralized Computing Andrew “bunnie”Huang, Ben Vandiver, Jeremy Brown, J.P. Grossman and Tom Knight Introduction 55
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Document Date: 2001-08-04 10:16:25

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File Size: 127,11 KB

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Company

MIT Artificial Intelligence Laboratory / MoSys / Xtensa Application Specific Microprocessor Solutions / TSMC / Tensilica Inc. / /

Facility

Q-cache port Virtual Memory Subsystem / Stanford University / /

IndustryTerm

large systems / software pipelining / software pipelines / manufacturing yields / source-responsible network protocol / reconfigurable hardware / process technology scenario / law runs / individual chips / technology du jour. / deep sub-micron technology / manufacturing processes / /

Organization

MIT / Stanford University / /

Person

Tom Knight / Ben Vandiver / Jeremy Brown / /

Position

garbage collector / thread scheduler / IP Thread Scheduler / head data Implementation / programmer / /

ProgrammingLanguage

Java / /

RadioStation

Core / /

SportsLeague

Stanford University / /

Technology

semiconductor / virtual machine / network protocol / Q-Machine Overview processor / Java / RISC processor / Grant W. CMOS Technology / caching / random access / SRAM / operating system / virtual memory / source-responsible network protocol / deep sub-micron technology / /

URL

www.mosys.com / /

SocialTag