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Computer architecture / Central processing unit / Virtual memory / CPU cache / Cache / Translation lookaside buffer / 64-bit / Address space / Memory management unit / Computing / Computer hardware / Computer memory


--03 April 13, 2000 Multistriped Addressing J.P. Grossman, Jeremy Brown, Andrew Huang, Tom Knight
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Document Date: 2001-05-16 17:41:21


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City

Node / /

Company

IBM / /

Facility

Computer Science Massachusetts Institute of Technology Cambridge / /

IndustryTerm

large scale shared memory systems / largescale systems / good parallel algorithms / possible solution / coherency protocol / cache-coherent and cacheless shared memory systems / coherent systems / cache-coherent systems / monolithic processor / /

Organization

Institute of Technology Cambridge / Project Aries Technical Memo ARIES-TM-03 Artificial Intelligence Laboratory Department of Electrical Engineering / Massachusetts Institute of Technology / /

Person

Nicholas P. Carter / Robert Alverson / John Keen / John Heinlein / Marco Fillo / Todd C. Mowry / Anoop Gupta / Richard Simoni / William J. Dally / John Chapin / Stephen W. Keckler / James Laudon / Richard Lethin / Nick Carter / David Ofelt / Andrew Huang / Burton Smith / Daniel Lenoski / Allan Perterfield / Jeffrey Kuskin / Andrew Chien / Mark Heinrich / D. Scott Wills / Luis Stevens / Kourosh Gharachorloo / David Callahan / Mark Horowitz / John Hennessy / David Nakahira / Jeremy Brown / Deborah Wallach / Brian Koblenz / Joel Baxter / Chi-Keung Luk / Michael Noakes / Stuart Fiske / Andrew Chang / Ellen Spertus / /

Position

hardware designer / /

PublishedMedium

Communications of the ACM / /

Technology

good parallel algorithms / artificial intelligence / virtual memory / html / shared memory / Operating Systems / coherency protocol / FLASH / Parallel processing / /

URL

http /

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