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Central processing unit / Instruction set architectures / Branch predication / Instruction set / Tomasulo algorithm / Branch misprediction / Microarchitecture / DEC Alpha / Operand forwarding / Computer architecture / Computer hardware / Computing


Levo - A Scalable Processor With High IPC
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Document Date: 2003-08-25 17:41:38


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File Size: 316,53 KB

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Company

Engineering Northeastern University Computer Architecture Research Laboratory / Levo High IPC Solutions / /

Currency

pence / /

/

Facility

Branch Table Entries In Active Station / pipeline O / Active Station / Computer Engineering Microarchitecture Research Institute / In Active Station / University of Rhode Island / Dana Research Center Northeastern University / Levo Active Station / This station / /

IndustryTerm

digital systems / energy consumption / unscalable hardware / transistor chips / realistic processor / distributed and scalable hardware / /

Organization

University of Rhode Island / AI Access Foundation / Electrical and Computer Engineering Microarchitecture Research Institute / Northeastern University / Department of Electrical / Dana Research Center Northeastern University Boston / Instruction Fetch Unit / Department of Electrical and Computer / /

Person

Augustus K. Uht / /

Position

forward / /

ProgrammingLanguage

DC / /

ProvinceOrState

Prince Edward Island / Massachusetts / /

Technology

Alpha / realistic processor / artificial intelligence / transistor chips / conventional Tomasulo algorithm / simulation / /

SocialTag