| Document Date: 2007-02-05 17:45:15
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City R3000 / R4000 / R10000 / Mountain View / / Company Silicon Graphics Inc. / SSD/SSR LLP / Data General / DSM Systems / The Origin 2000 / Daniel Lenoski Silicon Graphics Inc. / / Currency pence / AMD / / / Event Product Issues / FDA Phase / / Facility bridge XIO / Port SysAD Mem XIO Craylink GB/s / Simply building / / IndustryTerm loaded systems / networks / certain system applications / contemporary commercial ccNUMA systems / performance computing industry / higher-level coherence protocol / parallel systems / hardware link-level protocol / arbitration protocols / interconnection network / faulty hardware / contemporary systems / software features / parallel applications / interconnect network / software programmable threshold register / software availability / bank / access protection rights / processors / large parallel applications / ccNUMA systems / cache coherence protocol / higher level message protocol / request network / reply network / go-back-n sliding window protocol / coherence protocols / lowlevel signalling protocol / software programmable routing / meta-routers / shootdown algorithm / router chip / per-processor / coherence protocol / link technology / contemporary ccNUMA systems / large systems / hub chip / low-inductance fuzz-button processor / particular devices / higher performance per processor / node solutions / / MarketIndex STREAM / / NaturalFeature Fibre Channel / / OperatingSystem Sequent / PIOs / / Organization Lynx Board / ASIC / Stanford / / Person XB IO NI PI / Inval Multicast / James Laudon / / / Position arbiter / Bulk head / Msg Ctrl Arbiter / scheduler / / Product SC / IS / SCI / packets / R10000 / hardware / / ProgrammingLanguage XTALK / / ProvinceOrState Maryland / California / / Technology 128 processor / R10000 processors / video on demand / 36 processor / SRAM / operating system / shared memory / SPIDER router / two processor / 6 Processors / 3.2 Cache Coherence Protocol The cache coherence protocol / 16 processors / same link technology / 64 Processor / four processor / Protocol Table R10000 processor / 32 Processor / DASH protocol / SCI coherence protocol / coherence protocol / 8 processor / SPIDER routers / two R10000 processors / 300-pin compression connector HUB chip / two separate processors / two Crossbow chips / 512 processors / DASH coherence protocol / low-inductance fuzz-button processor / Fibre Channel / DASH coherence protocols / directory-based protocol / six-ported router chip / four processors / 8 processors / two processors / high-speed router / SPIDER chip / R10000 processor / higher-level coherence protocol / 128 processors / ATM / 1024 processors / 64 processors / cache coherence protocol / 2 Main Memory/ Directory Router / 1 Hub Chip / Ethernet / 16 16 16 Half Size Router / Hub chip / ASIC / arbitration protocols / same lowlevel signalling protocol / caching / SDRAM / hardware link-level protocol / eight meta-routers / go-back-n sliding window protocol / 32 processors / higher level message protocol / SCSI / 10 16 processor / /
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The SGI Origin: A ccNUMA Highly Scalable Server James Laudon and Daniel Lenoski Silicon Graphics, Inc.