SoftFlow: A Middlebox Architecture for Open vSwitch Ethan J. Jackson, University of California, Berkeley; Melvin Walls, Penn State Harrisburg and University of California, Berkeley; Aurojit Panda, University of Californi

Source URL: www.usenix.org

• Computing
• Information and communications technology
• Computer network security
• Data transmission
• Network architecture
• Computer networking
• Internet architecture
• Networking hardware
• OpenFlow
• Open vSwitch
• Middlebox
• Forwarding information base

Cooperating Proof Attempts Giles Reger, Dmitry Tishkovsky, and Andrei Voronkov ? University of Manchester, Manchester, UK Abstract. This paper introduces a pseudo-concurrent architecture for first-order saturation-based

Source URL: www.cs.man.ac.uk

• Formal methods
• Theoretical computer science
• Complexity classes
• Automated theorem proving
• Vampire
• NP
• IP
• Mathematics
• Constraint programming
• Proof compression

Technical Report UW-CSEPorting Hyperkernel to the ARM Architecture Dylan Johnson University of Washington

Source URL: unsat.cs.washington.edu

• Computer architecture
• Computing
• System software
• Central processing unit
• ARM architecture
• Translation lookaside buffer
• Hypervisor
• Protection ring
• QEMU
• X86 virtualization
• Hyper-V
• Second Level Address Translation

An Efficient Hardware Architecture for Factoring Integers with the Elliptic Curve Method Jens Franke, Thorsten Kleinjung - University of Bonn Christof Paar, Jan Pelzl - University of Bochum Christine Priplata, Colin Stah

Source URL: www.hyperelliptic.org

• Cryptography
• Integer factorization algorithms
• Lenstra elliptic-curve factorization
• Quadratic sieve
• Elliptic-curve cryptography
• Elliptic curve
• Integer factorization
• General number field sieve
• RSA
• Trial division

A hybrid architecture for interactive verifiable computation Victor Vu, Srinath Setty, Andrew J. Blumberg, and Michael Walfish The University of Texas at Austin questions of the prover, and applies efficient tests to the

Source URL: www.pepper-project.org

Calibrating the Classifier: Siamese Neural Network Architecture for End-to-End Arousal Recognition from ECG Andrea Patan`e and Marta Kwiatkowska Department of Computer Science, University of Oxford

Source URL: qav.comlab.ox.ac.uk

• Artificial neural networks
• Computational neuroscience
• Applied mathematics
• Neuroscience
• Cybernetics
• Computational statistics
• Market research
• Deep learning
• Heart rate variability
• Emotion recognition
• Recurrent neural network
• Affective computing

DESIGN AND SOCIAL INNOVATION FOR THE DEVELOPMENT OF HUMAN SMART CITIES FRANCESCA RIZZO UNIVERSITY OF BOLOGNA, DEAPRTMENT OF ARCHITECTURE AND TERRITORIAL

Source URL: www.onurcobanli.com

Authors Introduction Kenji Doi Professor, Department of Global Architecture, Graduate School of Engineering, Osaka University

Source URL: www.iatss.or.jp

The SFRA: A Fixed Frequency FPGA Architecture by Nicholas Croyle Weaver B.A. (University of California at Berkeley) 1995

Source URL: www1.icsi.berkeley.edu

      Department of Architecture, “Federico II” University of Napoli PhD Program in Architecture

Source URL: resarc.se