| Document Date: 2007-09-14 13:31:04
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Company IBM / Ge / Intel / / / Facility Bulk-Partial bar / BulkNoOverlap bar / Josep Torrellas University of Illinois / / IndustryTerm interconnection network / invalidation-based cache coherence protocol / conventional systems / coherence protocols / compilation infrastructure / conventional lazy systems / coherence protocol / cache coherence protocol / Conventional eager systems / / MarketIndex FSM / / Organization Updated Word Bitmask Unit / University of Illinois / National Science Foundation / US Federal Reserve / / Person Luis Ceze / Ray Tracer / James Tuck / / Position vp / Safe WB / BDM Controller / RT / Signature Functional Units Controller / WB / Cache/Coherence Controller / / Product Bulk Disambiguation / Bulk / SPECint2000 applications / SPECint2000 / Bulk Disambiguation Module / / ProgrammingLanguage Java / RC / C++ / / Technology Cryptography / Java / Wsh / finite state machine / two processors / coherence protocol / invalidation-based cache coherence protocol / receiving processor / simulation / cache coherence protocol / CMP / coherence protocols / / URL http /
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Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/