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Electronic design / Wishbone / OpenCores / Semiconductor intellectual property core / Application-specific integrated circuit / Field-programmable gate array / VMEbus / Conventional PCI / System on a chip / Electronic engineering / Electronics / Computer buses


Document Date: 2011-06-07 09:12:49

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File Size: 898,65 KB

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Company

Silicore Corporation / Cadence Design Systems Inc. / /

Country

United States / /

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Facility

SLAVE Output Port / /

Holiday

national holiday / Thanksgiving / /

IndustryTerm

semiconductor technology / layout tool technology / target devices / target hardware / connector systems / synthesis tool / integration solution / hardware technology / system integration solutions / bus protocols / logic synthesis tools / /

Organization

FPGA / ASIC / Contents CHAPTER / OpenCores Organization / DATA ORGANIZATION / /

Person

Avi Shamli Rudolf Usselmann / Barry Rice John Rynearson Avi / Wade D. Peterson / Volker Hetzer Magnus Homann Brian / Ray Alderman Yair Amitay Danny / Brian Hurt Linus Kirk Damjan / Marc Delvaux Miha Dolenc Volker / Danny Cohan Marc Delvaux Miha / Kirk Damjan Lampret Wade / Richard Herveille / /

Position

author / System Arbiter / original author / priority arbiter / round-robin arbiter / General / /

ProgrammingLanguage

Verilog / /

Technology

semiconductor / FPGA / RAM / ASIC / underlying semiconductor technology / Verilog / System-on-Chip / 1.3 Handshaking Protocol / bus protocols / WISHBONE System-on-Chip / ASIC production chips / hardware technology / VHDL / layout tool technology / Handshaking protocol / /

URL

www.paperdirect.com / www.opencores.org / www.kinkos.com / www.silicore.net/wishbone.htm / /

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