Friedberg / IBM / ON SEMICONDUCTOR / AMD / SEMICONDUCTOR MANUFACTURING / McGraw-Hill / Intel / /
Country
Japan / United Kingdom / /
Currency
USD / / /
Event
Business Partnership / /
Facility
University of Illinois / /
Holiday
Assumption / /
IndustryTerm
deep submicron technologies / technology scales / nanometer technologies / bank / technology generation / supply distribution network / Variation makes designing processors / technology generations / alpha power law / individual chip / possible applications / processor chip / /
Organization
Defense Advanced Research Projects Agency / University of Illinois / National Science Foundation / Department of Computer Science / Cambridge Univ. / /
Person
Jun Nakano / C. Spanos / Y. Cao / J. Rabaey / Abhishek Tiwari / J. Cain / Brian Greskamp / J. Xiong / V / R. Wang / Using Shockley Model / /
Position
A. General / driver / model for process variation / representative / model / Cao / /
Product
Opteron / /
PublishedMedium
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING / /
Technology
alpha / 32-nm technology / deep submicron technologies / 32-nm technologies / Variation makes designing processors / mean chip / individual chip / nanometer technologies / processor chip / Opteron processor / simulation / SRAM / Digital Object Identifier / pdf / integrated circuit / /
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 21, NO. 1, FEBRUARY[removed]VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects