Back to Results
First PageMeta Content
Regression analysis / Computer memory / MOSFET / Normal distribution / Dynamic random-access memory / Standard deviation / Threshold voltage / Systematic error / Errors and residuals in statistics / Statistics / Data analysis / Measurement


VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects ∗ Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R. Sarangi, Abhishek Tiwari and Josep Torrellas University of Illinois at Urb
Add to Reading List

Document Date: 2008-08-29 19:33:45

Open Document

File Size: 341,26 KB

Share Result on Facebook

City

Austin / Vienna / /

Company

Cambridge University Press / IBM Japan / Synopsys / AMD / Intel / John Wiley & Sons / /

Country

Austria / India / /

Facility

University of Virginia / Josep Torrellas University of Illinois / /

Holiday

Assumption / /

IndustryTerm

nm technologies / multicore chips / technology scales / nm technology / analytical solution / clumsy packet processors / supply distribution network / nm technology node / possible applications / predictive technology model / manufacturing processes / processor chip / 32nm technology / nanometer technologies / technology generation / deep-submicron technology / Variation makes designing processors / technology generations / individual chip / near-future technologies / /

Organization

Cambridge University / National Science Foundation / Foundation for Statistical Computing / University of Virginia / University of Illinois / /

Person

Jun Nakano / Y. Cao / P. Friedberg / W. Zhao / J. Rabaey / S. Datta / Abhishek Tiwari / Approach Dlogic / M. Metz / Brian Greskamp / P.J. Ribeiro Jr. / Robert Chau / C. Spanos / J. Kavalieros / M. Doczy / J. Cain / P.J. Diggle / R. Wang / /

Position

predictive technology model for sub-45nm design exploration / microarchitecture-aware model for parameter variation / General / model for parameter variation / novel model for process and temperature variation / Cao / representative / model / /

Product

Vth / Vth0 / /

ProvinceOrState

Virginia / Prince Edward Island / /

Technology

alpha / clumsy packet processors / self-tuning DVS processor / multicore chips / individual chip / lithography / processor chip / SRAM / pdf / deep-submicron technology / 32 nm technologies / Variation makes designing processors / dielectric / Urbana-Champaign http /

URL

http /

SocialTag