First Page | Document Content | |
---|---|---|
Date: 2013-09-27 01:18:40Computing Computer architecture Data compression Microprocessors Video compression Video acceleration Image compression H.262/MPEG-2 Part 2 Microarchitecture Macroblock Multi-core processor | 21st International Conference on VLSI Design Watermarking Video Clips with Workload Information for DVS Yicheng Huang Samarjit Chakraborty Ye WangAdd to Reading ListSource URL: www.smcnus.orgDownload Document from Source WebsiteFile Size: 651,09 KBShare Document on Facebook |