Date: 2012-12-31 04:25:31Software engineering Computing Models of computation Software Finite automata Finite-state machine Transition system XC Verilog Clock Presentation Specification and Description Language | | IF: An Intermediate Representation for SDL and its Applications Marius Bozga , Jean-Claude Fernandez , Lucian Ghirvu , Susanne Graf , Jean-Pierre Krimm , Laurent Mounier and Joseph Sifakis VERIMAG, Centre Equation, 2 aAdd to Reading ListSource URL: www-verimag.imag.frDownload Document from Source Website File Size: 247,10 KBShare Document on Facebook
|