<--- Back to Details
First PageDocument Content
Central processing unit / Intel iAPX 432 / CPU cache / Benchmark / Microcode / Pointer / ARM architecture / Microarchitecture / Reduced instruction set computing / Computer architecture / Computer hardware / Computing
Date: 2004-09-28 16:07:48
Central processing unit
Intel iAPX 432
CPU cache
Benchmark
Microcode
Pointer
ARM architecture
Microarchitecture
Reduced instruction set computing
Computer architecture
Computer hardware
Computing

Performance Effects of Architectural Complexity in the Intel 432 ROBERT P. COLWELL

Add to Reading List

Source URL: www.princeton.edu

Download Document from Source Website

File Size: 3,29 MB

Share Document on Facebook

Similar Documents

On Access Checking in Capability-Based Systems1 Richard Y. Kain Carl E. Landwehr  University of Minnesota

On Access Checking in Capability-Based Systems1 Richard Y. Kain Carl E. Landwehr University of Minnesota

DocID: 19zP6 - View Document

Memory Segmentation to Support Secure Applications Student: Jonathan Woodruff Supervisor: Simon W. Moore Project Lead: Robert N. M. Watson University of Cambridge, Computer Laboratory

Memory Segmentation to Support Secure Applications Student: Jonathan Woodruff Supervisor: Simon W. Moore Project Lead: Robert N. M. Watson University of Cambridge, Computer Laboratory

DocID: 15uUP - View Document

iAPX 86,88, 186 MICROPROCESSORS PART I

iAPX 86,88, 186 MICROPROCESSORS PART I

DocID: 4WlG - View Document

Performance Effects of Architectural Complexity in the Intel 432 ROBERT P. COLWELL

Performance Effects of Architectural Complexity in the Intel 432 ROBERT P. COLWELL

DocID: 22PJ - View Document

PDF Document

DocID: 6HJ - View Document