| Document Date: 2014-07-15 09:55:26
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City VENICE / / Company Altera / Microsoft / / / Facility store Kernel / University of Cambridge / Y X store / / IndustryTerm window algorithms / software pipelining / typical biological network / parallel applications / strip mining / level dataparallel algorithms / serious parallel applications / vector processing / vector unit hardware / licensed commercial product / fpga-based vector processors / Hardware/software / vector co-processor / host scalar processor / neural networks / given search region / search region / soft vector processor / computing / hardware developer / software pipeline / vector processor / soft vector processors / digital signal processing / heavyweight solution / / MarketIndex SAXPY / / Organization University of Cambridge / / Person Matthew Naylor / Morgan Kaufmann / / Position designer / programmer / / Product II processor / II / / ProgrammingLanguage C / C++ / / Technology high-level dataparallel algorithms / soft vector processors / neuroscience / FPGA / sliding-window algorithm / vector co-processor / fpga-based vector processors / Sliding window algorithms / host scalar processor / VectorBlox MXP Matrix Processor / FPGA system / machine learning / simulation / NIOS-II processor / soft vector processor / DSP / BlueVec soft vector processor / VENICE soft vector processor / VENICE Vector Processor / / URL http /
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Rapid codesign of a soft vector processor and its compiler Matthew Naylor and Simon W. Moore Computer Laboratory, University of Cambridge, UK {matthew.naylor,simon.moore}@.cl.cam.ac.uk Abstract—Despite a decade of acti