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CPU cache / Cache / Central processing unit / Computer memory / Virtual LAN / Internet Protocol / Packet Processing / Traffic flow / Transmission Control Protocol / Computing / Network architecture / Computer architecture


The Shunt: An FPGA-Based Accelerator for Network Intrusion Prevention Nicholas Weaver Vern Paxson
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Document Date: 2006-12-27 02:45:54

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File Size: 135,19 KB

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City

Monterey / Philadelphia / London / /

Company

FPGA MAC Group / Computer-Communication Networks / Xilinx / TRW / /

Country

United States / United Kingdom / /

Currency

USD / /

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Event

Person Communication and Meetings / /

Facility

port Gbps Phy / We pipeline / Stanford University / International Computer Science Institute / Shunt port / port Ethernet NIC / University of California / Ethernet port / /

IndustryTerm

network intrusion prevention systems / search operation / click modular router / Internet access link / parallel intrusion detection applications / considerable hardware / wide area network / prototype shunting software / software host / hardware device / packet processing operation / prevention systems / hardware+software path / hardware-plus-software-interface path / packet processors / reconfigurable hardware / network processing tasks / software packet processing elements / packet processing / Web Traffic / software routers / network processing applications / tcp/udp bandwidth measurement tool / intrusion prevention systems / assorted software tools / high-speed processing / computing / network processing / encryption algorithm / hardware/software path / depth-first-search / /

OperatingSystem

Linux / /

Organization

US Department of Energy / National Science Foundation / International Computer Science Institute / University of California / Berkeley / office of Science / Gonzalez International Computer Science Institute / Stanford University / /

Person

Greg Watson / Scott Campbell / Jonathan Turner / Stephen Lau / Aditya Akella / Nicholas Weaver / Tal Garfinkel / Scott Crosby / Dan Boneh / Ronald L. Rivest / Michale Freedman / Ioannis Sourdis / Robin Sommer / W. Wilinger / V / Curt Freeland / Eli Dart / Mike Attig / Proto Flags / John Lockwood / Dan Ellis / Sarang Dharmapurikar / Nick McKeown / Burton Bloom / Dan Wallach / Kyle Wheeler / Christian Kreibich / Martin Casado / Stuart Staniford / Todd Sproull / Weidong Cui / Click / Dionisios Pnevmatikatos / Haoyu Song / Vern Paxson / Lambert Schaelicke / Nicholas Weaver Vern Paxson Jose / /

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Position

Buffer Header Extract Arbiter / manager / Linux driver / CNET driver / memory arbiter / Ethernet driver / driver for the NetFPGA board / arbiter / cache manager / Ethernet General / forward / memory controller / controller / /

Product

Virtex 2 Pro FPGA / /

ProgrammingLanguage

C++ / /

ProvinceOrState

Manitoba / Pennsylvania / California / /

SportsLeague

Stanford University / /

Technology

FPGA / LAN / Linux / API / MAC address / block cipher / RC5 encryption algorithm / SRAM / udp / shared memory / SSL / Operating Systems / WAN / writing software routers / IP protocol / encryption / Ethernet / load balancing / HTTP / packet processors / Parallel Processing / /

URL

http /

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