| Document Date: 2013-02-07 18:21:05
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City PCIe Gen1x4 / Multiport / San Jose / / Company Cyclone V FPGAs / Taiwan Semiconductor Manufacturing Company / PCIe / Registered Altera Corporation / Altera Corporation / Intel / / Country Taiwan / / Event Natural Disaster / FDA Phase / / IndustryTerm 40LP technology / route algorithms / software enhancements / portable devices / low-power applications / changes to any products / interconnect protocol / audio-video products / low standby power applications / external memory interface solutions / semiconductor products / storage area networks / software application / / OperatingSystem Microsoft Windows / / Organization ID TLP / U.S. Patent and Trademark Office / / Person Elias Ahmed / Avalon read / Avalon Bus / / Position hb / Power Monitor DDR3 x40 Hard Memory Controller / Write Datapath User Logic I/O Block Controller / DDR3 memory controller / hard memory controller / Manager / Low-Power Device Architecture Hard Memory Controller / memory controller / controller / Product Marketing Manager / / Product Gen1x4 / PowerPlay / PCIe Interfaces / DDR3 / Cyclone V / / ProvinceOrState Manitoba / California / / Technology semiconductor / FPGA / route algorithms / 40LP technology / series processor / GUI / / URL www.altera.com/literature/wp/wp-01169-high-speed-memory.pdf / www.altera.com/common/legal.html / www.altera.com/devices/fpga/cyclone-v-fpgas/cyv-index.jsp / www.altera.com / www.altera.com/literature/an/an456.pdf / www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdf / /
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Implementing Efficient Low-Power PCIe Interfaces with Low-Cost FPGAs WP[removed]White Paper