![Computer architecture / Cache / Central processing unit / Microprocessors / Computer memory / CPU cache / Stencil code / Loop nest optimization / Opteron / POWER5 / Cell / Multi-core processor Computer architecture / Cache / Central processing unit / Microprocessors / Computer memory / CPU cache / Stencil code / Loop nest optimization / Opteron / POWER5 / Cell / Multi-core processor](https://www.pdfsearch.io/img/e1ee1edc80c5a943003c7cd338a00a68.jpg) Date: 2012-09-06 23:58:43Computer architecture Cache Central processing unit Microprocessors Computer memory CPU cache Stencil code Loop nest optimization Opteron POWER5 Cell Multi-core processor | | OPTIMIZATION AND PERFORMANCE MODELING OF STENCIL COMPUTATIONS ON MODERN MICROPROCESSORS‡ KAUSHIK DATTA†, SHOAIB KAMIL∗†, SAMUEL WILLIAMS∗†, LEONID OLIKER∗, JOHN SHALF∗, KATHERINE YELICK∗† Abstract. StAdd to Reading ListSource URL: crd.lbl.govDownload Document from Source Website File Size: 2,78 MBShare Document on Facebook
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