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Formal methods / Digital electronics / Hardware description languages / Clock signal / Electrical circuits / Flip-flop / Static timing analysis / Clock / Synchronization / Electronic engineering / Electronics / Electromagnetism


Microsoft Word - CummingsSNUG2001SJ_AsyncClk_rev1_2.doc
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Document Date: 2005-06-20 14:45:28

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File Size: 183,16 KB

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City

San Jose / /

Company

RTL / Synopsys / Sunburst Design Inc. / /

/

IndustryTerm

static timing analysis tool / synchronization applications / potential solution / static timing analysis tools / /

Organization

ASIC / /

Person

Clifford E. Cummings / Steve Golson / /

Position

non-compliant designer / designer / engineer / /

ProgrammingLanguage

Verilog / /

Technology

ASIC / Verilog / simulation / /

SocialTag