| Document Date: 2007-07-26 15:26:10
Open Document File Size: 626,33 KBShare Result on Facebook
City Austin / / Company Reduce AG / IBM / Toshiba / Sony / / / Event Reorganization / / Facility Sri Sathya Sai University / / IndustryTerm few other algorithms / reduction algorithm / above algorithms / alternate algorithms / regular cache-based processors / binomial tree algorithm / heterogeneous multi-core processor / barrier algorithms / heterogeneous multicore processor / store on-chip / / OperatingSystem Linux / / Organization Florida State University / Sri Sathya Sai University / / Position XDR memory controller / scheduler / memory controller / / ProvinceOrState Manitoba / Prince Edward Island / / Technology eight processors / regular cache-based processors / above algorithms / 3 Algorithms / RAM / Broadband / local store on-chip / following three algorithms / four processors / heterogeneous multicore processor / sixteen processors / Linux / Cell processors / binomial tree algorithm / four barrier algorithms / tree-based algorithms / TREE algorithm / shared memory / DIS algorithms / reduction algorithm / Cell processor / same chip / five algorithms / /
SocialTag |
Microsoft Word - HiPC07.final.doc