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The Dataflow Schedule Graph and Applications to Heterogeneous Computing Systems Hsiang-Huang Wu Department of Electrical & Computer Engineering, and Institute for Advanced Computer Studies University of Maryland
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Document Date: 2014-09-30 21:01:44

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File Size: 161,17 KB

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Company

SDSG / A. As / /

Country

Austria / /

Event

Man-Made Disaster / /

Facility

Salzburg University of Applied Sciences / Advanced Computer Studies University of Maryland College Park / /

IndustryTerm

heterogeneous computing systems / target processor / given processor / given target processor / signal processing systems / dataflow tools / individual target processors / signal processing / heterogeneous signal processing system design / conventional processor / particular scheduling tool / digital signal processing / energy / /

Organization

Salzburg University of Applied Sciences / University of Maryland College Park / Heterogeneous Computing Systems Hsiang-Huang Wu Department of Electrical & Computer Engineering / /

Person

Huang Wu / /

Position

referenced actor / run-time scheduler / actor / corresponding fi actor / application graph actor / corresponding actor / scheduler / homogeneous synchronous dataflow actor / loop actor / Marshall / /

ProgrammingLanguage

RC / /

ProvinceOrState

Maryland / Georgia / RA / /

Technology

FPGA / target processor / load balancing / given processor / conventional processor / given target processor / individual target processors / DSP / /

SocialTag