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Xeon / CPU cache / Multi-core processor / Intel Core / Hyper-threading / Nehalem / Hash join / Computing / Computer hardware / Computer architecture


Improving Main Memory Hash Joins on Intel Xeon Phi Processors: An Experimental Approach Saurabh Jha1 Bingsheng He1 Mian Lu2 Xuntao Cheng3 Huynh Phung Huynh2 1 2
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Document Date: 2015-01-10 21:50:55

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File Size: 1,68 MB

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City

STAR IHPC / /

Company

MiB 977 MiB Experimental Setup Hardware / Prefetching(default distance) Software / Creative Commons / Xeon Phi Software / Intel / Hardware Conscious Join Hardware / /

Country

Singapore / /

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Facility

Nanyang Technological University / /

IndustryTerm

hardware systems / software optimizations / hardware oblivious algorithms / query processing / hardwareoblivious and hardware-conscious algorithms / processor technologies / software approaches / multi-core processors / co-processors / 5110P co-processor / basic hardware / outperformed hardware oblivious algorithms / namely hardware / conscious algorithms / /

OperatingSystem

L3 / /

Organization

Graduate School / VLDB Endowment / Nanyang Technological University / Singapore / Nanyang Technological University / International Criminal Court / /

Position

tackle / Major / scheduler / /

ProvinceOrState

Hawaii / /

RadioStation

Core / /

Technology

hardware oblivious algorithms / existing CPU-optimized algorithms / still outperformed hardware oblivious algorithms / 5110P co-processor / RAM / load balancing / processor technologies / partitioning algorithm / hardwareoblivious and hardware-conscious algorithms / /

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http /

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