Back to Results
First PageMeta Content
Electromagnetism / Integrated circuits / Electronic design automation / Arbiter / Asynchronous system / Network On Chip / Asynchronous circuit / Digital electronics / Synchronization / Electronic engineering / Electrical engineering / Electrical circuits


November 2008 Synchronizer Reliability in the Next Generation of SoC with Multiple Clocks (SYRINGE) EP/C007298/1 Alex Yakovlev (Principal Investigator), Gordon Russell, David J.Kinniment, Newcastle University
Add to Reading List

Document Date: 2008-11-12 14:13:03

Open Document

File Size: 40,94 KB

Share Result on Facebook

City

Manchester / Princeton / Munich / Tampere / London / Grenoble / Hillsborough / /

Company

Asynchronous Systems / IEEE CS Press / Wiley and Sons / Elastix Corp. / Intel / VLSI Systems / Strategic CAD Labs / /

Country

Germany / United States / United Kingdom / Finland / Spain / /

Currency

GBP / /

/

Facility

University of Newcastle / Mr Dike / Mr Charles E. Dike / C.E. Dike / /

IndustryTerm

reconfigurable neural network / nanometer technologies / self-timed event processors / 130nm chip / /

Organization

Newcastle University / University of Newcastle / School of EECE / /

Person

M. Renaudin / Gordon Russell / David J / D. Potop-Butucaru / G. Russell / A.Bystrov / N. Minas / B. Caillaud / M. Marshall / K. Heron / Dasgupta / Jun Zhou / D. Shang / Alex Yakovlev / Alessandro / Heron / S. Dasgupta / J. Zhou / A. Yakovlev / Marc Renaudin / John Bainbridge / Jordi Cortadella / /

Position

Principal Investigator / D.J. / arbiter / Professor / /

PublishedMedium

Electronic Notes in Theoretical Computer Science / /

Technology

FPGA / self-timed event processors / SYRINGE1 chip / 130nm chip / Elastic Clock technology / off chip / neural network / System-on-Chip / nanometer technologies / Flash / /

URL

http /

SocialTag