<--- Back to Details
First PageDocument Content
FlexRay / CAN bus / AUTOSAR / Time division multiple access / Time-Triggered Protocol / Static timing analysis / Scheduling / Network performance / Vector Informatik / Technology / Computing / Computer networks
Date: 2012-10-31 05:01:40
FlexRay
CAN bus
AUTOSAR
Time division multiple access
Time-Triggered Protocol
Static timing analysis
Scheduling
Network performance
Vector Informatik
Technology
Computing
Computer networks

Microsoft Word - embedded_world_08_final_marek_jersak_080109_03_mj.doc

Add to Reading List

Source URL: www.symtavision.com

Download Document from Source Website

File Size: 1,39 MB

Share Document on Facebook

Similar Documents

Proc. Asia South Pacific Design Automation Conf. (ASP-DAC), Shanghai, China, vol. 1, Jan. 2005, pp. I/2-I/7.  Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw, an

Proc. Asia South Pacific Design Automation Conf. (ASP-DAC), Shanghai, China, vol. 1, Jan. 2005, pp. I/2-I/7. Opportunities and Challenges for Better Than Worst-Case Design Todd Austin, Valeria Bertacco, David Blaauw, an

DocID: 1rqwy - View Document

IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. XX, Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

IEEE TRANSACTIONS ON COMPUTERS, VOL. 63, NO. XX, Application-Adaptive Guardbanding to Mitigate Static and Dynamic Variability

DocID: 1qV9r - View Document

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling ∗ 2  Sibin Mohan1, Frank Mueller1 , William Hawkins2 , Michael Root3 , Christopher Healy3 and David Whalley4

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage Scaling ∗ 2 Sibin Mohan1, Frank Mueller1 , William Hawkins2 , Michael Root3 , Christopher Healy3 and David Whalley4

DocID: 1fIXS - View Document

Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users FPGA 2 VIVA11000-ILT (v1.0)

Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users FPGA 2 VIVA11000-ILT (v1.0)

DocID: 1fE9q - View Document

Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints FPGA 3 FPGA-VSTAXDC-ILT (v1.0)

Vivado Design Suite Static Timing Analysis and Xilinx Design Constraints FPGA 3 FPGA-VSTAXDC-ILT (v1.0)

DocID: 1eT6Z - View Document