<--- Back to Details
First PageDocument Content
Computing / Computer architecture / Concurrent computing / Formal methods / Theoretical computer science / Cache coherency / Instruction set architectures / Concurrency / TLA+ / Model checking / Cache coherence / Specification language
Date: 2010-09-11 18:46:20
Computing
Computer architecture
Concurrent computing
Formal methods
Theoretical computer science
Cache coherency
Instruction set architectures
Concurrency
TLA+
Model checking
Cache coherence
Specification language

Checking Cache-Coherence Protocols with TLA+ Rajeev Joshi HP Labs, Systems Research Center, Palo Alto, CA. Leslie Lamport Microsoft Research, Mountain View, CA.

Add to Reading List

Source URL: rjoshi.org

Download Document from Source Website

File Size: 113,32 KB

Share Document on Facebook

Similar Documents

CS:APP2e Web Aside ASM:X87: X87-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron June 5, 2012

CS:APP2e Web Aside ASM:X87: X87-Based Support for Floating Point∗ Randal E. Bryant David R. O’Hallaron June 5, 2012

DocID: 1ru2k - View Document

HARVARD RESEARCH GROUP   OpenVMS: When Continuous Availability Really Matters Compaq’s OpenVMS and IBM’s z/OS (formerly OS/390) are generally regarded in the

HARVARD RESEARCH GROUP  OpenVMS: When Continuous Availability Really Matters Compaq’s OpenVMS and IBM’s z/OS (formerly OS/390) are generally regarded in the

DocID: 1rn8I - View Document

Gyrokinetic Particle-in-Cell Optimization on Emerging Multi- and Manycore Platforms Kamesh Madduria , Eun-Jin Imb , Khaled Z. Ibrahima , Samuel Williamsa , St´ephane Ethierc , Leonid Olikera a Computational

Gyrokinetic Particle-in-Cell Optimization on Emerging Multi- and Manycore Platforms Kamesh Madduria , Eun-Jin Imb , Khaled Z. Ibrahima , Samuel Williamsa , St´ephane Ethierc , Leonid Olikera a Computational

DocID: 1rlO7 - View Document

Document:   ! ! !

Document: ! ! !

DocID: 1rhja - View Document

eSi-3200 – 32-bit, low-cost & low-power CPU EnSilica’s eSi-3200 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs with on-chip memories. The eSi-3

eSi-3200 – 32-bit, low-cost & low-power CPU EnSilica’s eSi-3200 CPU IP core is an extremely small, low-cost and low-power processor ideal for integration into ASIC and/or FPGA designs with on-chip memories. The eSi-3

DocID: 1rbpk - View Document