| Document Date: 2014-01-10 19:15:42
Open Document File Size: 925,42 KBShare Result on Facebook
City San Diego / / Company On-Chip Networks / Qualcomm Inc. / Synopsys / RTL / Vinci / Intel Corporation / / / Event Product Issues / Analyst Recommendation / Reorganization / / Facility University of Illinois / stable Vdd / / IndustryTerm network energy consumption / board hardware / energy-inefficient designs / relative energy consumption / substantial network energy / average energy reduction / particular router / slowest routers / multiprocessor chip / energy density / energy overhead / technology parameters / memory systems / chip manufacturers / energy savings / proposed low-cost solution / energy / negligible energy / off-chip / interconnection network / relative energy savings / virtual channel router / technology-based parameters / substantial energy reductions / energy consumption / to current chips / average energy / target process technology / 8x8 mesh network / manufacturing-testing time / bank / baseline chip / aggressive process technology / manufacturing time / close-by devices / tradingoff energy efficiency / energy-efficient design / manufacturing equipment / typical protocols / large multi-core chip / energy efficiency / darker routers / slowest router / 4x4 mesh network / substantial energy savings / large chip / cache coherence protocol / static energy / less energy efficient / / OperatingSystem LDOs / / Organization National Science Foundation / Reliability Management Unit / University of Illinois / / Person Asit Mishra / ‡ Jianping / Amin Ansari / Amin Ansari / † Asit / / Position representative / / Product Vdd / 8x8 Tangle system / Tangle NoC / messages / message / paths / path / 8x8 Tangle / / ProgrammingLanguage Verilog / / RadioStation Core / / Technology Alpha / 3 Router / NoC router / chip design / multiprocessor chip / two routers / 100 router / 1 16 routers / baseline chip / particular router / large chip / NoC routers / aggressive process technology / one router / 16 routers / 2 Router / 1 0.9 1.08 1.06 16 routers / cache coherence protocol / Vdd tuning algorithm / 4 routers / 100 routers / slowest routers / virtual channel router / one processor / Enabling Technology / Verilog / Error 1.0E-03 Router / Voltage Tuning Algorithm / -06 0.9 1.0E-09 Router / 36 routers / network routers / 8 routers / target process technology / simulation / slowest router / 1 router / 3-stage router / 64 routers / CAD / /
SocialTag |
Tangle: Route-Oriented Dynamic Voltage Minimization for Variation-Afflicted, Energy-Efficient On-Chip Networks ∗ Amin Ansari,† Asit Mishra,‡ Jianping Xu,‡ Josep Torrellas † ‡ Intel Corporation † Universit