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Hardware verification languages / Aldec / Logic design / SystemVerilog / Verilog / SystemC / VHDL / E / Simulink / Electronic engineering / Hardware description languages / Electronic design automation


Riviera-PRO™ Advanced Verification Verification Platform Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench pro
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Document Date: 2015-05-05 17:04:52

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City

Benefits Standards / /

Company

Synopsys / Altera / RTL / Covergroup / Aldec Inc. / Auto / Xilinx / Agilent / /

/

Facility

Library Managers / /

IndustryTerm

Built-in debugging tools / simulation optimization algorithms / coverage analysis tools / /

OperatingSystem

Linux / Microsoft Windows / Microsoft Vista / /

/

Position

Design Management HDL Editor / Server Farm Manager / /

Product

Riviera / /

ProgrammingLanguage

Perl / Tcl/Tk / MATLAB / Verilog / C / Simulink / C++ / /

Technology

Encryption / DESIGN VERIFICATION / FPGA / Server Farm / Verilog / Linux / 2005 IEEE Encryption / Perl / simulation / simulation optimization algorithms / VHDL / GUI / /

URL

www.aldec.com / /

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