![Central processing unit / Instruction set architectures / Branch predictor / Alpha 21264 / CPU cache / Out-of-order execution / Register renaming / Microarchitecture / DEC Alpha / Computer architecture / Computer engineering / Computer hardware Central processing unit / Instruction set architectures / Branch predictor / Alpha 21264 / CPU cache / Out-of-order execution / Register renaming / Microarchitecture / DEC Alpha / Computer architecture / Computer engineering / Computer hardware](https://www.pdfsearch.io/img/e34f4c07338deda78ababc7322ba1583.jpg)
| Document Date: 2003-06-05 15:33:55 Open Document File Size: 263,37 KBShare Result on Facebook
Company AMD / / Facility Computer Science University of Virginia Charlottesville / / IndustryTerm in-order processors / recent processors / out-of-order processors / wide-issue processors / / MarketIndex IPC / SPEC / / Organization Princeton University / Computer Science University of Virginia Charlottesville / / Person Kevin Skadron / Virginia Charlottesville / / Position representative / / Product HydraScalar / / ProgrammingLanguage Perl / FP / / ProvinceOrState New Jersey / Wisconsin / Virginia / / Technology Alpha / out-of-order processors / real processor / virtual machine / perl / simulation / wide-issue processors / Even in-order processors / /
SocialTag |