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And-inverter graph
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1	Microsoft Word - speedup10.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-04-27 18:18:38 Digital electronics Electrical circuits Electronic design And-inverter graph Field-programmable gate array Static timing analysis Logic synthesis Propagation delay Retiming Electronic engineering Electronic design automation Formal methods
2	Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720 Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-01 19:34:13 Boolean network American International Group Science Economy of New York City Electronics Diagrams And-inverter graph Electronic design automation
3	Microsoft Word - power18.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2009-07-10 18:57:40 Electronic design Integrated circuits And-inverter graph Field-programmable gate array Logic synthesis Logic gate Sequential logic Power optimization CMOS Electronic engineering Electronic design automation Digital electronics
4	Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-01 19:34:23 Digital electronics Diagrams Logic in computer science And-inverter graph Retiming Logic synthesis Formal verification Combinational logic Standard cell Electronic engineering Electronic design automation Formal methods
5	Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-01 16:05:11 Digital electronics Electronic design Formal methods And-inverter graph Retiming Logic synthesis Automatic test pattern generation Field-programmable gate array Sequential logic Electronic engineering Electronics Electronic design automation
6	Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2005-05-01 15:18:03 Electronics Boolean algebra Diagrams Algebraic logic And-inverter graph Logic synthesis Boolean function Circuit Topology Electronic engineering Electromagnetism Electronic design automation
7	Cutless FPGA Mapping Alan Mishchenko Sungmin Cho Satrajit Chatterjee Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-09-14 17:01:40 And-inverter graph Tree Trie Directed acyclic graph R-tree Graph theory Diagrams Field-programmable gate array
8	Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-02-27 20:55:14 Electronics Diagrams Boolean algebra And-inverter graph Canonical form Logic synthesis Circuit Boolean function Topology Electronic engineering Electromagnetism Electronic design automation
9	Microsoft Word - haig09.doc Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2008-03-23 19:52:58 Electronic design automation Electronic design Logic in computer science And-inverter graph Retiming Logic optimization Combinational logic Automatic test pattern generation Logic programming Electronic engineering Formal methods Digital electronics
10	Symmetry Detection for Large Boolean Functions using Circuit Representation, Simulation, and Satisfiability Jin S. Zhang1 Alan Mishchenko2 Robert Brayton2 Malgorzata Chrzanowska-Jeske1 1 Department of ECE Add to Reading List Source URL: www.bvsrc.org Language: English - Date: 2006-05-08 11:02:36 Electronic engineering Electronic design automation Formal methods Diagrams Symmetry And-inverter graph Binary decision diagram Boolean satisfiability problem Symmetry in mathematics Mathematics Theoretical computer science Boolean algebra