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Digital electronics / Electronic design / And-inverter graph / Retiming / Logic optimization / Automatic test pattern generation / Combinational logic / Formal verification / Logic programming / Electronic engineering / Formal methods / Electronic design automation


Microsoft Word - haig14.doc
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Document Date: 2008-05-20 20:12:25


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File Size: 100,88 KB

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City

Recording Window / A SAT / /

Company

IBM / CNF / ABC / AIG / Actel / IEEE D&T Comp / Synopsys / AMD / Altera Corp. / Xilinx / Intel / /

/

Facility

University of California / /

IndustryTerm

final networks / synthesis tool / combinational network / synthesis tools / sequential synthesis algorithm / implementation technology / logic networks / technology mapping / technology mapping algorithm / synthesis algorithm / sequential mapping combining technology / pre-processing / verification tool / /

MarketIndex

QUIP / /

OperatingSystem

GNU/Linux / /

Organization

National Science Foundation / UC Berkeley / University of California / Berkeley / U.S. Securities and Exchange Commission / Sequential Verification Alan Mishchenko Robert Brayton Department of EECS / /

Person

J. Baumgartner / V / Alan Mishchenko Robert Brayton / Jin Zhang / Van Eijk / H. Mony / V / /

/

Position

manager / manager aig / designer / class representative / representative / candidate pairs / /

Product

AIGs / /

Technology

sequential mapping combining technology / FPGA / jpeg / Linux / implementation technology / retiming-based technology mapping algorithm / pdf / http / synthesis algorithm / simulation / sequential synthesis algorithm / CAD / /

URL

http /

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