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Electronic design automation / Digital electronics / Logic in computer science / Electrical circuits / And-inverter graph / Retiming / Automatic test pattern generation / Formal verification / Combinational logic / Electronic engineering / Formal methods / Theoretical computer science


Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS, University of California, Berkeley
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Document Date: 2007-10-02 14:31:33

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IBM / CNF / Synopsys / ABC / Altera / AIG / Xilinx / Intel / Actel / /

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Event

Reorganization / /

Facility

University of California / /

IndustryTerm

technology mapping / verification algorithms / iterative processing / combinational network / improved search strategies / technology mapping algorithm / frames network / proposed synthesis algorithms / convert networks / sequential network / /

MarketIndex

set 50 industrial / /

Organization

PI PO / University of California / Berkeley / U.S. Securities and Exchange Commission / Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko Department of EECS / /

Person

J. Baumgartner / V / A. Kuehlmann / V / Stephen Jang / Robert Brayton Alan Mishchenko / H. Mony / V / /

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Position

same driver / straight-forward / representative / wb / /

Technology

FPGA / Ethernet / RAM / verification algorithms / partitioning algorithm / proposed algorithms / simulation / technology mapping algorithm / retiming-based technology mapping algorithm / proposed synthesis algorithms / presented algorithms / CAD / /

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http /

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