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Electronic design automation / Electrical circuits / And-inverter graph / Diagrams / Retiming / Automatic test pattern generation / Scan chain / Combinational logic / Sequential logic / Electronic engineering / Formal methods / Digital electronics


Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton
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Document Date: 2008-07-28 20:26:28

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City

ISEC / Edinburgh / San Jose / /

Company

IBM / CNF / Synopsys / ABC / EECS Xilinx Inc. / Altera / RTL / AIG / Xilinx / Intel / Actel / /

Country

Scotland / /

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Facility

University of California / /

IndustryTerm

insurance purposes / technology mapping / verification algorithms / iterative processing / combinational network / technology mapping algorithm / frames network / convert networks / /

MarketIndex

set 20 industrial / /

Organization

National Science Foundation / Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Department of EECS Xilinx Inc. / UC Berkeley / University of California / Berkeley / U.S. Securities and Exchange Commission / /

Person

J. Baumgartner / V / Alan Mishchenko Michael Case Robert / Jin Zhang / Lut Lev Scl / Michael Case Robert Brayton / H. Mony / V / Stephen Jang / /

Position

same driver / straight-forward / representative / /

ProvinceOrState

California / /

Technology

FPGA / RAM / verification algorithms / partitioning algorithm / simulation / technology mapping algorithm / retiming-based technology mapping algorithm / CAD / /

URL

http /

SocialTag