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Boolean algebra / Diagrams / Digital electronics / And-inverter graph / Binary decision diagram / Logic optimization / Model checking / Boolean function / Logic synthesis / Electronic engineering / Electronic design automation / Formal methods


FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton Department of EECS, University of California, Berkeley {alanmi, satrajit, jiejiang
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Document Date: 2005-04-01 15:19:32

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File Size: 225,89 KB

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building Reduced Ordered Binary Decision Diagrams / Microelectronics Center / University of California / /

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final optimized network / post-processing step / potential applications / intermediate networks / software implementation / technology mapping / number applications / intermediate network / improved technology mapping / final networks / technology mapping step / post processing step / technology mapper / gate network / synthesis tools / search space / feasible solutions / include exploring other potential applications / /

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Windows XP / /

Organization

MARCO Focus Center for Circuit System Solution / National Science Foundation / Robert Brayton Department of EECS / UC Berkeley / University of California / Berkeley / Microelectronics Center of North Carolina / Univ. of California / /

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A. Kuehlmann / V / Robert Brayton / Santa Barbara / Roland Jiang / Alan Mishchenko / /

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designer / manager / representative / /

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North Carolina / California / /

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proposed algorithm / improved technology / laptop computer / 6.3 Technology / simulation / Graph-based algorithms / CEC algorithms / 4 Functional Reduction Algorithm / CAD / detected using simulation / derived using bit-parallel simulation / /

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