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SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang
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Document Date: 2007-04-23 22:32:02

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City

San Jose / /

Company

CNF / ABC / Altera Corp. / AIG / Intel / EE Xilinx Inc. / /

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Facility

S. Plaza / EECS University of California / /

IndustryTerm

logic network / by-product / technology-dependent resynthesis / logic networks / technology mapping / large network / heterogeneous algorithms / combinational logic networks / large networks / combinational network / good-quality technology / improved windowing algorithm / resynthesis algorithm / post processing script / /

MarketIndex

set 20 industrial / /

MusicGroup

ABC / /

Organization

Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Stephen Jang Department of EE Xilinx Inc. / UC Berkeley / PI PO / University of California / Berkeley / Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Stephen Jang Department of EE Xilinx Inc. / National Taiwan University / /

Person

Alan Mishchenko Robert Brayton / Roland Jiang Stephen Jang / Jie-Hong Roland Jiang Stephen / Robert Brayton Jie-Hong Roland / /

ProvinceOrState

California / /

TVStation

TFO / /

Technology

previous algorithm / FPGA / RAM / improved windowing algorithm / proposed algorithm / good-quality technology / windowing algorithm / http / simulation / pdf / resynthesis algorithm / CAD / /

URL

http /

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