| Document Date: 2006-02-27 20:55:14
Open Document File Size: 327,42 KBShare Result on Facebook
Company IBM / Fujitsu / Algebraic Re-Writing / MVSIS Group / Lehman / Intel / Strategic CAD Labs Intel Corporation / / / Facility building BDDs / / IndustryTerm technology mapping scripts / lossless synthesis intermediate networks / conventional matching algorithm / pre-processing step / technology-independent synthesis algorithms / simplified matching algorithm / intermediate networks / technology mapping problem / technology mapping / area-flow algorithm / intermediate network / multilevel network / depth-first search starting / combinational network / technology mapping algorithm / final network / faster matching algorithm / larger search space / technology mapper / pre-computing / good initial multi-level network / search space / re-writing explore different search spaces / / Organization Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department / MARCO Focus Center for Circuit and System Solution / / Person A. Kuehlmann / V / / Position NPN-equivalence representative / NPN-representative / NPN-canonical representative / canonical representative / representative / variable permutation using representative / ” Proc / Senator / N-equivalence representative / / Technology FPGA / simplified Boolean matching algorithm / synthesis algorithms / matching algorithm / simplified matching algorithm / API / simplified / Boolean matching algorithm / 22 Technology / area-flow algorithm / faster matching algorithm / Boolean matching algorithm / simulation / technology mapping algorithm / Wavefront technology / conventional matching algorithm / simplified cut-based Boolean matching algorithm / LUT-based FPGA technology / CAD / / URL http /
SocialTag |
Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS