| Document Date: 2005-05-01 15:18:03
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Company IBM / MVSIS Group / Lehman / Intel / Strategic CAD Labs Intel Corporation / / / Facility building BDDs / MCNC library / / IndustryTerm lossless synthesis intermediate networks / pre-processing step / technology-independent synthesis algorithms / simplified matching algorithm / intermediate networks / technology mapping problem / technology mapping / intermediate network / area-flow algorithm / simplified cut-based boolean matching algorithm / multilevel network / combinational network / technology mapping algorithm / boolean matching algorithm / final network / faster matching algorithm / larger search space / technology mapper / pre-computing / good initial multi-level network / search space / / Organization Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department / / Person A. Kuehlmann / V / / Position NPN-equivalence representative / NPN-representative / NPN-canonical representative / canonical representative / variable permutation using representative / ” Proc / N-equivalence representative / / Technology FPGA / RAM / simplified Boolean matching algorithm / mapping algorithm / synthesis algorithms / matching algorithm / simplified matching algorithm / API / simplified / Boolean matching algorithm / 22 Technology / area-flow algorithm / faster matching algorithm / boolean matching algorithm / simulation / technology mapping algorithm / Wavefront technology / simplified cut-based boolean matching algorithm / LUT-based FPGA technology / CAD / / URL http /
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Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton X. Wang T. Kam Department of EECS