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Digital electronics / Diagrams / Logic in computer science / And-inverter graph / Retiming / Logic synthesis / Formal verification / Combinational logic / Standard cell / Electronic engineering / Electronic design automation / Formal methods


Verification after Synthesis Alan Mishchenko Robert Brayton Department of EECS
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Document Date: 2006-05-01 19:34:23

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City

Chicago / /

Company

IBM / ABC / Altera / AIG / Intel / /

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Facility

T. Villa / EECS University of California / /

IndustryTerm

intermediate networks / software implementation / technology mapping / delay-optimal technology mapping / intermediate network / public-domain systems / final networks / search spaces / synthesis tool / technology mapping algorithm / final network / synthesis tools / technology mappings / sequential verification algorithms / verification tool / /

MarketIndex

IWLS / /

MusicGroup

ABC / /

Organization

National Science Foundation / EECS University / University of California / Berkeley / Synthesis Alan Mishchenko Robert Brayton Department / /

Person

L. Trevillyan / C. L. Berman / Alan Mishchenko Robert Brayton / W. H. Joyner / Jr. / A. Darringer / A. Kuehlmann / V / /

Position

manager / history manager / General / wb / /

TVStation

TFO / /

Technology

ethernet / FPGA / RAM / sequential verification algorithms / API / simulation / technology mapping algorithm / retiming-based technology mapping algorithm / pdf / CAD / /

URL

http /

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