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City New York / Chicago / / Company IBM / ABC / Altera / AIG / John Wiley & Sons Inc. / Intel / optimized assuming an AIG / detected using an AIG / / / Facility University of California / / IndustryTerm logic network / resubstitution algorithm / logic synthesis algorithms / multi-level logic networks / window construction algorithm / technology dependent mapping / technology independent/dependent algorithms / software synthesis / synthesis algorithms / technology-dependent resynthesis / optimization algorithms / Software implementation / technology mapping / industrial applications / greedy algorithm / technology mapping algorithm / computing / cut computation algorithm / typical network / logic synthesis applications / / MusicGroup ABC / / NaturalFeature Shannon / / Organization MARCO Focus Center for Circuit System Solution / National Science Foundation / UC Berkeley / Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department / University of California / Berkeley / US Federal Reserve / / Person W. H. Joyner / Jr. / / Position manager / wb / representative / / Product AIGs / / ProgrammingLanguage R / L / / ProvinceOrState Illinois / New York / California / / TVStation TFO / / Technology FPGA / resubstitution algorithm / RAM / synthesis algorithms / rewriting algorithm / 4-input rewriting algorithm / windowing algorithms / proposed algorithms / logic synthesis algorithms / retiming-based technology mapping algorithm / pdf / ethernet / window construction algorithm / optimization algorithms / http / simulation / 3 Logic synthesis algorithms / cut computation algorithm / CAD / computed using exhaustive simulation / / URL http / SocialTag 
Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton EECS Department, University of California, Berkeley, CA 94720