![Central processing unit / Computer memory / Runahead / Cache / CPU cache / Branch predictor / Microarchitecture / Memory hierarchy / Speculative execution / Computer architecture / Computer hardware / Computer engineering Central processing unit / Computer memory / Runahead / Cache / CPU cache / Branch predictor / Microarchitecture / Memory hierarchy / Speculative execution / Computer architecture / Computer hardware / Computer engineering](https://www.pdfsearch.io/img/69a73424ed7debdfb93e867d099c4ea9.jpg) Date: 2010-12-27 00:10:17Central processing unit Computer memory Runahead Cache CPU cache Branch predictor Microarchitecture Memory hierarchy Speculative execution Computer architecture Computer hardware Computer engineering | | CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAUAdd to Reading ListSource URL: iacoma.cs.uiuc.eduDownload Document from Source Website File Size: 631,46 KBShare Document on Facebook
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