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Central processing unit / Computer memory / Runahead / Cache / CPU cache / Branch predictor / Microarchitecture / Memory hierarchy / Speculative execution / Computer architecture / Computer hardware / Computer engineering


CAVA: Using Checkpoint-Assisted Value Prediction to Hide L2 Misses LUIS CEZE, KARIN STRAUSS, JAMES TUCK, and JOSEP TORRELLAS University of Illinois at Urbana–Champaign and JOSE RENAU
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Document Date: 2010-12-27 00:10:17

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File Size: 631,46 KB

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City

Urbana-Champaign / New York / /

Company

Checkpoint / IBM / ACM Inc. / Intel / /

Country

United States / /

Currency

USD / /

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Facility

JOSE RENAU University of California / University of Illinois / JOSEP TORRELLAS University of Illinois / University of California / /

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IndustryTerm

conventional processors / scientific applications / irregular applications / software prefetching / conventional superscalar processors / multiprocessor systems / aggressive superscalar processor / coherence protocol / cache coherence protocol / conventional processor / superscalar processors / /

Organization

Explicitly Addressed / University of Illinois / University of California / Santa Cruz / National Science Foundation / L1 MSHR / Explicitly Addressed MSHR / JOSE RENAU University / Champaign and JOSE RENAU University / /

Person

LUIS CEZE / Comparator / KARIN STRAUSS / Josep Torrellas / JAMES TUCK / /

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Position

L2 controller / VP / L2 cache controller / General / producer / head / /

ProvinceOrState

Illinois / California / New York / /

Technology

conventional superscalar processors / aggressive superscalar processor / conventional processor / coherence protocol / CAVA processor / cache coherence protocol / /

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