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Central processing unit / Branch predictor / CPU cache / Microarchitecture / Memory-level parallelism / Register renaming / Superscalar / DEC Alpha / Computer performance / Computer architecture / Computer hardware / Computer engineering


Energy-Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions A. Gellert1 G. Palermo2
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Document Date: 2010-02-24 17:04:56


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State University of New York / Store Queues / University of Sibiu / University of Wisconsin / /

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simplescalar tool / required energy budget / proposed energy-aware load value predictor / micro-processors / Overall energy consumption improvement / energy consumption / overall energy reduction / energy degradation / energy aware value prediction / less additional hardware / energy speed-up / frequency processors / energy reduction / energy / /

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Department of Computer Science / Computer Science and Engineering Department / State University of New York at Binghamton / Politecnico di Milano / University of Sibiu / IEEE Computer Society / University of Wisconsin / /

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Alpha / micro-processor / simulation / operating systems / high-frequency processors / Integrated Circuit / /

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