RICE UNIVERSITY Exploiting Instruction-Level Parallelism for Memory System Performance by Vijay S. Pai

Source URL: rsim.cs.uiuc.edu

Insight into Application Performance Using Application-Dependent Characteristics Waleed Alkohlani1 , Jeanine Cook2 , and Nafiul Siddique1 1 Klipsch School of Electrical and Computer Engineering,

Source URL: www.dcs.warwick.ac.uk

• Cache
• Central processing unit
• Computer memory
• Computer architecture
• Parallel computing
• CPU cache
• Locality of reference
• Benchmark
• Microarchitecture
• Instruction set
• Instruction-level parallelism
• Draft:Cache memory

Comparing and Combining Read Miss Clustering and Software Prefetching


Source URL: research.ac.upc.edu

• Software pipelining
• CPU cache
• Cache
• Parallel computing
• Instruction-level parallelism
• Computer engineering
• Computer hardware
• Computer memory
• Computing

A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM Yoongu Kim Vivek Seshadri Donghyuk Lee

Source URL: users.ece.cmu.edu

• Dynamic random-access memory
• Synchronous dynamic random-access memory
• CAS latency
• SDRAM latency
• Serial presence detect
• Memory controller
• DDR3 SDRAM
• Random-access memory
• CPU cache
• Computer memory
• Computer hardware
• Computing

Why GPUs? Robert Strzodka (MPII), Dominik Göddeke (TUDo), Dominik Behr (AMD) PPAM 2009 – Conference on Parallel Processing and Applied Mathematics Wroclaw, Poland, September 13-16, 2009

Source URL: gpgpu.org

• Computer hardware
• Instruction-level parallelism
• Stream processing
• Central processing unit
• Speedup
• GPGPU
• Very long instruction word
• Computer memory
• Computing
• Parallel computing
• Computer architecture

Scalable 
 Cache Miss Handling 
 For High MLP James Tuck, Luis Ceze, and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu

Source URL: iacoma.cs.uiuc.edu

• Computer engineering
• Computer memory
• Microprocessors
• CPU cache
• Cache
• Memory-level parallelism
• Runahead
• Intel Core
• Microarchitecture
• Computer architecture
• Computer hardware
• Central processing unit

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction Luis Ceze, Karin Strauss, James Tuck, Jose Renau† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, kstrauss, jtuck, torrellas}@c

Source URL: iacoma.cs.uiuc.edu

• Central processing unit
• Runahead
• CPU cache
• Microprocessors
• Branch predictor
• Memory-level parallelism
• Microarchitecture
• Instruction window
• Hardware scout
• Computer architecture
• Computer hardware
• Computer engineering

Scalable Cache Miss Handling for High Memory-Level Parallelism

Source URL: iacoma.cs.uiuc.edu

• Central processing unit
• Microprocessors
• Computer memory
• CPU cache
• Cache
• Runahead
• Multi-core processor
• Microarchitecture
• Memory-level parallelism
• Computer hardware
• Computer architecture
• Computing

Are We Ready for High Memory-Level Parallelism? Luis Ceze, James Tuck and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign Email: {luisceze,jtuck,torrella}@cs.uiuc.edu

Source URL: iacoma.cs.uiuc.edu

• Central processing unit
• Computer memory
• Cache
• CPU cache
• Runahead
• Microprocessors
• Memory-level parallelism
• Microarchitecture
• AMD 10h
• Computer architecture
• Computer hardware
• Computer engineering

Improving Memory Latency Aware Fetch Policies for SMT Processors Francisco J. Cazorla1 , Enrique Fernandez2 , Alex Ram´ırez1 , and Mateo Valero1 1 2

Source URL: personals.ac.upc.edu

• Central processing unit
• Microprocessors
• Parallel computing
• Threads
• CPU cache
• Multithreading
• Instruction-level parallelism
• Branch predictor
• Multi-core processor
• Computing
• Computer architecture
• Computer hardware