SYNERGISTIC CACHING IN SINGLE-CHIP MULTIPROCESSORS a dissertation submitted to the department of electrical engineering and the committee on graduate studies

Source URL: cva.stanford.edu

• Cache
• Computer architecture
• Central processing unit
• Computer engineering
• Microprocessors
• CPU cache
• Microarchitecture
• Computer memory
• Computer hardware
• Computing

RESOURCE MANAGEMENT IN SINGLE-CHIP MULTIPROCESSORS a dissertation submitted to the department of computer science and the committee on graduate studies

Source URL: cva.stanford.edu

Design Tradeoffs for Tiled CMP On-Chip Networks ∗ James Balfour , William J. Dally Computer Systems Laboratory Stanford University

Source URL: cva.stanford.edu

• Computer networking
• Network performance
• Throughput
• Network switch
• Routing
• Packet switching
• Channel
• Router
• Asynchronous Transfer Mode
• Computing
• Electronic engineering
• Network architecture

Scalable Opto-Electronic Network (SOENet)
 Amit K. Gupta, William J. Dally, Arjun Singh, and Brian Towles

Source URL: cva.stanford.edu

• Electronics
• Switched fabric
• Fat tree
• InfiniBand
• Routing
• Topology
• Ethernet
• Clos network
• Node
• Network topology
• Computing
• Network architecture

WMF2EPS 1.31 : WMF->EPS conversion for indep_contrib.emf

Source URL: cva.stanford.edu

• Throughput
• Routing algorithms
• Computing
• Wireless networking
• Telecommunications engineering
• Network performance
• Routing
• Routing protocols

Microsoft Word - vlsi2004_main.doc

Source URL: cva.stanford.edu

• Oscillators
• Electronic design
• Radio electronics
• Integrated circuits
• Digital electronics
• Voltage-controlled oscillator
• Phase-locked loop
• Jitter
• Analog-to-digital converter
• Electronic engineering
• Electronics
• Electromagnetism

Delay and Buffer Bounds in High Radix Interconnection Networks Abstract queues is a known hard problem. The difficulty in analysis primarily arises from the fact that the traffic processes do

Source URL: cva.stanford.edu

• Electronic engineering
• Queuing delay
• Quality of service
• Traffic flow
• Queueing theory
• Throughput
• Leaky bucket
• TCP global synchronization
• Network performance
• Statistics
• Management

A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN.

Source URL: cva.stanford.edu

• Routing
• Flow control
• Network On Chip
• Wormhole switching
• Throughput
• Network switch
• Router
• Traffic flow
• Channel
• Network architecture
• Computing
• Electronic engineering

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 11, NOVEMBERLow-Power Area-Efficient High-Speed I/O Circuit Techniques

Source URL: cva.stanford.edu

• Electronic design
• Integrated circuits
• Digital electronics
• Oscillators
• Electronic circuits
• Inverter
• Analog-to-digital converter
• Phase-locked loop
• CMOS
• Electronic engineering
• Electronics
• Electromagnetism

Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139

Source URL: cva.stanford.edu

• Network performance
• OSI protocols
• Inter-process communication
• Traffic flow
• Throughput
• Network architecture
• Transmission Control Protocol
• Wormhole switching
• Packet switching
• Computing
• Computer networking
• Streaming