1![PS-1 Ultra Low-Power High-Speed Flexible Probabilistic Adder for Error-Tolerant Applications PS-1 Ultra Low-Power High-Speed Flexible Probabilistic Adder for Error-Tolerant Applications](https://www.pdfsearch.io/img/8c99737e07044a0904590834aef99a56.jpg) | Add to Reading ListSource URL: www.bpti.ltLanguage: English - Date: 2013-12-16 08:28:50
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2![194 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 3, NO. 2, MARCH 1992 Virtual-Channel Flow Control William J. Dally, Member, IEEE 194 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL. 3, NO. 2, MARCH 1992 Virtual-Channel Flow Control William J. Dally, Member, IEEE](https://www.pdfsearch.io/img/559de0afee72cfbd0cc41ad4d21210be.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:16:32
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3![/afs/ir.stanford.edu/users/a/r/arjuns/work/research/TOR_NN/RESULTS/HILAT/VAL_13.eps /afs/ir.stanford.edu/users/a/r/arjuns/work/research/TOR_NN/RESULTS/HILAT/VAL_13.eps](https://www.pdfsearch.io/img/151aaabf3fa3e9166ac24507e541bc4d.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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4![IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks IEEE TRANSACTIONS ON COMPUTERS, VOL. 40, NO. 9, SEPTEMBERExpress Cubes: Improving the Performance of k-ary n-cube Interconnection Networks](https://www.pdfsearch.io/img/d175c45bfca6533afc5e3f80626cf07f.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:17:54
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5![A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN. A DELAY MODEL FOR ROUTER MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES, ENABLING ROUTER ARCHITECTS TO OPTIMIZE NETWORK PERFORMANCE BEFORE BEGINNING ACTUAL DETAILED DESIGN.](https://www.pdfsearch.io/img/8fe4b9445d3877b6071582c30fc53563.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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6![Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139 Virtual- Channel Flow Controll William J. Dally Artificial Intelligence Laboratory and Laboratory for Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts 02139](https://www.pdfsearch.io/img/2e5f967dec4e25349581c558ff87d3c6.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:20:06
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7![Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu Route Packets, Not Wires: On-Chip Interconnection Networks William J. Dally and Brian Towles Computer Systems Laboratory Stanford University Stanford, CA 94305 {billd,btowles}@cva.stanford.edu](https://www.pdfsearch.io/img/de08b4d041c91d8d3f8d840e04211f58.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:04
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8![775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks 775 IEEE TRANSACTIONS ON COMPUTERS, VOL. 39, NO. 6, JUNE 1990 Performance Analysis of k-ary n-cube Interconnection Networks](https://www.pdfsearch.io/img/9753997ad4e817a86aa0ade501f1fe29.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2008-04-03 14:18:56
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9![A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally A Delay Model for Router Micro-architectures Li-Shiuan Peh William J. Dally](https://www.pdfsearch.io/img/5a3b7818b4b7de44938af9cda6347d53.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:05
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10![In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally In Proceedings of the 6th International Symposium on High-Performance Computer Architecture, Toulouse, France, January 10-12, 2000. ppFlit-Reservation Flow Control Li-Shiuan Peh William J. Dally](https://www.pdfsearch.io/img/5cac236d376ee6b02d9687d8341d0781.jpg) | Add to Reading ListSource URL: cva.stanford.eduLanguage: English - Date: 2005-12-01 13:38:05
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