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Microtechnology / Chemical-mechanical planarization / Etching / Back end of line / Copper interconnect / Through-silicon via / Wafer / Chemical vapor deposition / Three-dimensional integrated circuit / Semiconductor device fabrication / Electronics / Technology


Robust TSV Via­Middle and Via­Reveal Process Integration Accomplished through Characterization and Management of Sources of Variation
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Document Date: 2014-05-27 18:47:55

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File Size: 3,32 MB

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Company

IBM / CMP / TSVs / Micron December / Xilinx / Bob Linke Applied Materials Inc. / /

Country

Malta / United States / /

Currency

USD / /

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IndustryTerm

subsequent processing / metal / few applications / carrier type/diameter / frontend-of-line device / end products / multi-core processors / 3D chip / via-reveal applications / interposer applications / electronics / process-integration technology / chemical / material properties management / energy / /

Person

Anthony Chan / Rohit Mishra / Kedar Sapre / Jennifer Tseng / Brad Eaton / John Dukovic / Rao Yalamanchili / Graw Hill Book / John Hua / Sherry Xia / Glen Mori / /

ProvinceOrState

California / /

PublishedMedium

Semiconductor International / the IBM Journal / /

Technology

FPGA / process-integration technology / dielectric / lithography / 3D chip / Integrated Circuits / CVD / chemical vapor deposition / /

URL

www.imicronews.com/lectureArticle.asp?id=7916 / /

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