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Results: 99

#	Item
41	Input-Covering Schedules for Multithreaded Programs Tom Bergan Luis Ceze Dan Grossman Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2013-08-07 18:27:55
42	ColorSafe: Architectural Support for Debugging and Dynamically Avoiding Multi-variable Atomicity Violations Brandon Lucia† Luis Ceze† Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2010-04-14 00:55:31 Concurrency control Data management Memory management Debugging Software bug C dynamic memory allocation Pointer CPU cache MySQL Computing Data Transaction processing
43	Finding Concurrency Bugs with Context-Aware Communication Graphs Brandon Lucia Luis Ceze Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2009-10-01 12:43:18 Data Information Graph theory Data management Transaction processing Lock Serializability Graph CPU cache Computing Concurrency control Software bugs
44	Low-Level Detection of Language-Level Data Races with LARD Benjamin P. Wood Luis Ceze Dan Grossman Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2014-01-09 16:38:09
45	Integrated 3D-Stacked Server Designs for Increasing Physical Density of Key-Value Stores Anthony Gutierrez Michael Cieslak Ronald G. Dreslinski Luis Ceze† Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2014-03-01 12:40:42
46	A Case for System Support for Concurrency Exceptions Luis Ceze, Joseph Devietti, Brandon Lucia and Shaz Qadeer† University of Washington {luisceze, devietti, blucia0a}@cs.washington.edu Abstract Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2009-03-19 20:35:38 Data management Data Linearizability Lock Transactional memory Parallel computing Atomicity Serializability Exception handling Computing Concurrency control Transaction processing
47	Bulk Disambiguation of Speculative Threads in Multiprocessors∗ Luis Ceze, James Tuck, C˘alin Cas¸caval† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, jtuck, torrellas}@cs.uiuc.edu http:/ Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2007-09-14 13:31:04 Computing Microprocessors Threads Parallel computing CPU cache Computer memory Multithreading Microarchitecture Threading Computer hardware Computer architecture Central processing unit
48	Deterministic Process Groups in dOS Tom Bergan Nicholas Hunt Luis Ceze Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2010-09-19 15:21:20 Concurrent computing Thread Concurrency control Determinism NL Indeterminism Monitor Deterministic system Shim Computing Computer programming Software engineering
49	Colorama: Architectural Support for Data-Centric Synchronization ∗ Luis Ceze, Pablo Montesinos, Christoph von Praun† and Josep Torrellas University of Illinois at Urbana-Champaign {luisceze, pmontesi, torrellas}@cs.u Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2007-09-14 13:31:03 Computer programming Critical section Lock Subroutine Linearizability Pointer Mutual exclusion Parallel computing Monitor Computing Concurrency control Software engineering
50	DeLorean: Recording and Deterministically Replaying Shared-Memory Multiprocessor Execution Efficiently∗ Pablo Montesinos, Luis Ceze† and Josep Torrellas Department of Computer Science University of Illinois at Urbana Add to Reading List Source URL: homes.cs.washington.edu Language: English - Date: 2008-03-26 12:09:20 Central processing unit Chunk CPU cache Parallel computing C dynamic memory allocation Computer memory Computing Computer hardware