| Document Date: 2010-04-10 06:56:21
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City Paris / / Company Thales group / NIOS Software / Elsevier Ltd. / RTL / CRC Press / / Country France / Italy / Singapore / / / Facility Prentice Hall / Technical University of Lodz / / IndustryTerm times less energy / hardware solution / pre-processing step / dilation algorithms / energy consumption / software algorithm / software coding style / software implementation / cost efficient device / software version / low power applications / purpose processor / image processing operations / simplest solution / power optimization tools / morphological algorithm / pre-processing stage / hardware algorithm / iris recognition algorithm / technology dependent / carrier mobility / energy / / Organization ASIC / Technical University of Lodz / US Federal Reserve / Beata MIKOVICOVA Institut Supérieur d’Electronique de Paris / / Person Andrzej Napieralski / Pixel / TORRES ESLAVA / / Position designer / first author / / Product SoC / Stratix III / / Technology FPGA / ADC / ASIC / software algorithm / Iris Recognition Algorithm The iris recognition algorithm / JTAG / dielectric / hardware algorithm / purpose processor / iris recognition algorithm / image processing / dilation algorithms / /
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