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Clock gating
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1	Power Reduction Through RTL Clock Gating By Frank Emnett and Mark Biegel Automotive Integrated Electronics Corporation Add to Reading List Source URL: www.eng.auburn.edu - Date: 2007-12-06 17:00:33
2	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 4, APRILDesign Flow for Flip-Flop Grouping in Data-Driven Clock Gating Add to Reading List Source URL: euler.ecs.umass.edu Language: English - Date: 2014-03-31 16:24:12 Digital electronics Electronic engineering Electronic design automation Electrical engineering Clock signal Digital systems Clock gating Energy conservation Gating Clock Flip-flop Power optimization
3	Temperature-Aware GPU Design Jeremy W. Sheaffer, Kevin Skadron, and David P. Luebke University of Virginia Dept. of Computer Science {jws9c, skadron, luebke}@cs.virginia.edu The Need for Temperature-Aware Design Add to Reading List Source URL: qsilver.cs.virginia.edu Language: English - Date: 2004-08-23 12:32:16 Computing Energy conservation Dynamic voltage scaling Clock gating Thermal management of electronic devices and systems GeForce 4 Series Multi-core processor Central processing unit Low-power electronics Computer hardware Electronic engineering Clock signal
4	A10 SO nly Allwinner Technology CO., Ltd. Add to Reading List Source URL: dl.linux-sunxi.org Language: English - Date: 2012-09-24 05:08:29 Interrupt Synchronous dynamic random-access memory Clock gating Programmable Interrupt Controller Computing Electronics Interrupts Electronic engineering Interrupt request
5	Datasheet Power Compiler Power Optimization in Design Compiler Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:51 Electromagnetism Digital electronics Power gating Clock gating Power optimization Power management Compiler Design flow Unified Power Format Electronic engineering Electronic design automation Electronics
6	Datasheet Synphony C Compiler High-Level Synthesis from C/C++ to RTL Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:31:02 High-level synthesis Logic synthesis SystemVerilog Synopsys Verilog Clock gating Field-programmable gate array Catapult C Compiler Electronic engineering Electronic design automation Hardware description languages
7	Datasheet DC Explorer Early RTL Exploration Accelerates Design Schedules Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:50 Design closure Register-transfer level Design flow Clock gating Integrated circuit design Electronic engineering Electronic design automation Physical design
8	Microsoft PowerPoint - 21_lines [Read-Only] Add to Reading List Source URL: www.hotchips.org Language: English - Date: 2013-07-27 23:40:39 Computer hardware Synchronization Clock signal Central processing unit Delay insensitive circuit Asynchrony Flip-flop Clock gating Pipeline Electronic engineering Electronics Digital electronics
9	Designing Low-Energy Embedded Systems from Silicon to Software, Part 1–Silicon Choices Add to Reading List Source URL: www.silabs.com Language: English - Date: 2015-02-21 21:17:41 Digital electronics Power gating CMOS Clock gating Dynamic voltage scaling Clock signal Silicon Laboratories Microcontroller Central processing unit Electronic engineering Electronics Electromagnetism
10	[EPC-43] How Software and Hardware Can Cooperate To Manage Power Consumption John Carbone, Express Logic, Inc. Add to Reading List Source URL: rtos.com Language: English - Date: 2009-04-06 22:49:47 Digital electronics Energy conservation Microcontrollers Central processing unit ARM architecture Power gating Sleep mode Power management Clock signal Electronic engineering Computer architecture Electronics

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